There are four basic operations in semiconductor processing, layering, patterning, doping, and heat treatments. Layering is the operation used to add thin layers to the surface of a semiconductor wafer. Patterning is the series of steps that results in the removal of selected portions of the layers added in layering. Doping is the process that puts specific amounts of dopants in the wafer surface through openings in the surface layers. Finally, heat treatments are the operations in which the wafer is heated and cooled to achieve specific results. Of these basic operations, patterning is typically the most critical, creating the surface parts of the devices that make up a circuit on the semiconductor wafer.
In some types of semiconductor fabrication, a hard mask is used in addition to the customary photoresist for patterning. The photoresist is initially patterned, and then a hard mask under the photoresist is etched where exposed through the photoresist, to become correspondingly patterned. This is shown by reference to FIGS. 1A and 1B. In FIG. 1A, a semiconductor device 100 being fabricated includes a polysilicon layer 102, a hard mask layer 104, and a photoresist layer 106. The hard mask layer 104 has an upper layer 104a and a lower layer 104b. The upper layer 104a may be oxide (SiO2), whereas the lower layer 104b may be SiON. An opening 108 has been created through the photoresist layer 106 via patterning, selectively exposing the hard mask layer 104 below.
In FIG. 1B, the hard mask layer 104 has been etched through the opening 108 in the photoresist layer 106, and the photoresist layer 106 subsequently removed, or stripped. Thus, the polysilicon layer 102 is exposed through the opening 108 that now extends through the hard mask layer 104. The polysilicon layer 102 can now be patterned, so that it, too, has a trench or hole corresponding to the opening 108. The etching of the hard mask layer 104 can sometimes undesirably result in the creation of a defect particle 110 within the opening 108, however. The defect particle 110 is usually embedded within the polysilicon layer 102. It may be made up of the material of the hard mask layer 104 and/or the material of the polysilicon layer 102.
The defect particle 110 is particularly disadvantageous because subsequent etching of the polysilicon layer 102 will result in the creation of a polysilicon bridge, meaning that the polysilicon layer 102 has been etched improperly. This is shown in FIG. 1C. Desirably, etching of the polysilicon layer 102 results in extension of the opening 108 over the indicated width 114. However, because the particle 110 partially blocks exposure of the polysilicon layer 102 through the opening 108, etching of the polysilicon layer 102 actually results in extension of the opening 108 over only the indicated width 112. An undesired polysilicon bridge 116 thus results.
The presence of such undesired polysilicon bridges ultimately reduces semiconductor device yield during device fabrication, which can be costly to the semiconductor foundry. The defect particle 110 is therefore desirably eliminated prior to polysilicon etching, between FIGS. 1B and 1C. Current approaches utilize APM cleaning and megasonic vibration. APM cleaning usually employs an ammonium hydroxide, hydrogen peroxide, and water mixture, which, along with megasonic vibration, removes the defect particle 110. However, this approach is itself disadvantageous, resulting in gate oxide integrity (GOI) failure.
Therefore, there is a need for another approach to remove defect particles from polysilicon surfaces that result from hard mask etching. Desirably such removal approach should not cause GOI failure, as APM cleaning and megasonic vibration do. For these reasons, as well as other reasons, there is a need for the present invention.